(1) Field of the Invention
The present invention relates to a method of fabricating an electronic discharge (ESD) protection device, and more particularly to a process of forming a non-silicide ESD device.
(2) Description of the Related Art
Electrostatic discharge (ESD) devices exists when a quite large voltage usually generated by suddenly is released triboelectricity (electricity caused when two materials are rubbed together). For example, a person taking an integrated circuit from its plastic wrapping material or walking across a room can generate voltage up to 2000V. Such an unintended discharge getting into a metal oxide semiconductor field effect transistor (MOSFET) can cause immediately huge damage to the circuit or subsequent early life failure. ESD devices will not work if the circuit is exposed under the normal control voltage. ESD devices will turn on to prevent the circuit from huge damage, only when the voltage is higher than the normal control voltage.
In recent years, the sizes of the individual semiconductor devices have continuously decreased so that the integrated circuit density on chips has dramatically increased. As the sizes of the capacitors become smaller, so as the resistance values of the MOS transistors are increasing, the operational speed of the IC devices is reduced, causing the performance problem. Therefore, so-called salicide process has been developed to reduce the resistance of the MOS transistors. Unfortunately, the salicide process will reduce the capacity of the ESD protection circuit, too.
In order to solve such problem, an ESD protection circuit without salicide that is incorporated with MOS transistors with salicide is proposed. Referring to FIGS. 1A.about.1D a conventional fabrication method of an ESD protection circuit without salicide formation is depicted. An oxide layer should be formed on the ESD devices to form the non-silicide ESD devices and an dielectric layer also should be formed by depositing an oxide layer under the top capacitor electrode. As mentioned above, the process of deposition oxide layer is used twice in the conventional fabrication method of an ESD protection circuit.
Referring now to FIG. 1A, the conventional fabrication method of an ESD protection circuit without silicide formation is depicted. A silicon substrate 10 with a layer of gate oxide and a layer of field oxide 20 is provided. A first doped polysilicon layer is formed on the substrate 10. After that, a layer of gate oxide and a first doped polysilicon layer are defined to form a gate oxide layer 60 and gate structures 50 at the ESD areas A, a gate oxide layer 61 and resistors 51 at resistance areas B, a gate oxide layer 62 and gate electrodes 52 at active areas C and a dielectric layer 63 and end capacitor electrodes 53 at capacitor areas D. Then, Sidewall spacers 70 are formed at the sidewall of the gate structures 50, the resistors 51, the gate electrodes 52 and the end capacitor electrodes 53. Next, a process of ion implantation is performed to form the lightly doped source/drain 40 regions (LDD) and doped areas 30.
Next, please refer to FIG. 1A again, a first layer of oxide 100 on the substrate 10 and a doped polysilicon layer are formed. After defining the top capacitor electrodes 90 at the capacitor areas C, the residual first layer of oxide 100a is patterned to form the dielectric layer between the top capacitor electrodes and the end capacitor electrodes, as shown in FIG. 1B.
Next, refer to FIG. 1C, a second oxide layer 110 is formed at the ESD areas, resistance areas B and capacitor areas D. The second oxide 110 of active areas C is removed for the following salicide process on the gate electrodes 52, source/drain regions 40 of the active areas C. The second oxide layer 110 is formed on the ESD areas A to prevent the salicidation. Finally, as shown in FIG. 1D, the silicide layer 81 is formed on the gate electrodes 52 and source/drain regions 40.
As mentioned above, in accordance with the prior art, two oxide layers (first oxide layer 100 and second oxide layer 110) should be formed. The first oxide layer 100 is deposited to form the dielectric layer 100a between the end capacitor electrodes 53 and top capacitor electrodes 90. The second oxide layer 110 is deposited to form the isolation during the salicide process.